Yagle performs the automatic generation of HDL descriptions, in Verilog or VHDL, from transistor-level netlists, by partitioning and analyzing the network of transistors. Tri-state nodes of the circuit are expressed as VHDL Bus. Latches and registers are expressed as conditioned statements within separate VHDL processes. The process is totally free of user intervention and does not require any pre-defined library. Nevertheless, a user-defined gate library can be provided in order to handle complex latches or analog circuitry.
The generated HDL descriptions can be used by common verification tools. Yagle allows functional modeling and verification of full and semi-custom designs, by logical simulation or equivalence checking.
Yagle's HDL descriptions are also compliant with synthesis tools requirements, and allow easy technology migration.
Yagle's unique ability to provide timing back-annotated HDL descriptions, close to physical implementation, enables the setup of solutions based on signal activity, such as power consumption or IR-drop analysis.
A hierarchical pattern-matching engine allows genuine treatment of analog cells. Its memory-array recognition capability enables Yagle to abstract Mbytes SRAMs in a matter of minutes.
The following diagram illustrates Yagle's integration in the design flow.
The most important features of Yagle are:
Yagle is able two generate HDL behavioral descriptions at different levels of abstraction.
Closest to physical implementation is a low-level HDL. Associated with this description, Yagle generates a correspondence table, that link electrical and logical names.
A high-level HDL is obtained by expression simplification and intermediary signals suppression.
A compact HDL can also be obtained by vectorization. The pattern-matching engine identifies the repetitive structures, such SRAM arrays, and vectorizes the HDL descriptions according to them.
The main applications of Yagle are:
The Yagle tool offers designers a revolutionary new strategy for the functional verification of their digital custom circuits, known as Functional Abstraction. Previous strategies for functional verification at the lowest level relied upon SPICE-like electrical simulations and were therefore limited to small circuit blocks. Functional Abstraction takes the task of behavioral verification to a higher level by directly extracting a simulatable RTL description from the transistor netlist by disassembly of the circuit.
The Yagle approach to circuit disassembly for functional abstraction can be defined as a partitioning of the transistor net-list, according to a limited number of generic rules. Each partition represents an extracted gate for which a behavioral description can be deduced. The result is a totally generic approach with a minimum of user intervention.
In the first phase, Yagle extracts the dual CMOS circuitry. In the second phase, Yagle builds the gate net-list for the remaining circuitry whilst performing functional analysis in parallel, in order to prevent the fabrication of false branches within a gate and to verify the behavior of the gate. This procedure allows Yagle to take into account the functional correlation in the surrounding circuitry. The depth of surrounding circuitry taken into account is adapted automatically within a maximum bound which can be specified by the user.