The use of automatic tools in the design of integrated circuits allows the generation of complex circuits made up of a large number of blocks of identical structure. In many cases these blocks represent a significant part of the circuit, and require a particular attention of the designer during verification in order to validate the structure generated by the automatic design tools.
The Yagle tool automatically generates a functional description without requiring any a priori knowledge of the circuit. This capability is ideal in the case of digital circuits made up of many diversified structures. However, rule-based recognition, the alternative to the automatic approach, is significantly more efficient in the handling of repetitive structures. Furthermore, pattern matching is the only way to cope with mixed analog / digital designs.
Embedded memory cores are the perfect example of the use of regular, repetitive structures. A large part of the design is made up of the arrays of memory cells together with analog blocks for pre-charging and amplification. Such designs can be represented by highly compact, hierarchical structural descriptions.
GNS allows the user to provide hierarchical abstraction rules in a similar way to the original structural description.
Hierarchical recognition of regular structure blocks from transistor level allow to perform faster validation on high complexity circuits. Performing the validation at transistor level guarantees the precision of the validation, since the transistor level is the most accurate description of the final circuit.
GNS provides the means for today's circuit designers to satisfy the demand for rapid time-to-market whilst enhancing the robustness of their validation strategy.
The most important application of the GNS tool are:
The GNS tool offers designers the possibility of writing generic rules to verify the structural integrity of all or part of their circuits. Each recognition rule is written in a syntax compatible with VHDL. The rules are fully hierarchical, allowing concise descriptions of complex structures. In addition, each rule can be made generic, meaning that interconnections of arbitrary numbers of components can be represented.
GNS combines functional and structural verification in a single tool. Structural verification is performed by the application of user-defined hierarchical rules, starting at the transistor-level. These rules, written in VHDL, specify interconnections of a fixed or arbitrary number of components. The structure of even complex circuit architectures can be fully described.
Behavioral models can be automatically generated even for totally generic structures. This is done by associating actions with the recognition rules. Each action is a small program, written by the user, in a subset of 'C' which dynamically generates the model based upon the sizes of the recognized structures.
With the addition of the GNS module, Yagle is a complete functional abstraction solution. This technology, coupled with the FCL technology to isolate basic building-blocks, allows rapid verification of the regular structures in a design using compact user-defined rules.
The circuit is automatically partitioned into regular and non-regular parts. Yagle calculates a functional model which seamlessly integrates with the models generated by GNS to allow simulation and verification of the complete design.