5. Design Flow Integration

5. 1. Transistor-Level Analysis

For a block up to 1M transistors, HITAS performs a flat transistor-level analysis, and generates a flat timing database of the block, taking into account the interconnect parasitics (RC networks).

5. 2. Full-Chip Analysis

In the hierarchical analysis mode, HITAS uses existing timing views of instantiated blocks to work out the timing database of the whole circuit, taking into account the interconnects between blocks.

5. 3. Input Files

5. 3. 1. Netlist

.spi flat transistor extraction from the layout in SPICE format, possibly with interconnect parasitics and coupling capacitances
.cdl hierarchical schematic CDL/SPICE
.spi hierarchical netlist in SPICE format
.vhdl hierarchical netlist in structural VHDL format
.vlg, .v hierarchical netlist in structural Verilog format

5. 3. 2. Parasitics

.dspf, .spf interconnect parasitics and coupling capacitances back-annotation in DSPF/SPF format
.spef interconnect parasitics and coupling capacitances back-annotation in SPEF format

5. 3. 3. Technology

bsim3 SPICE format, BSIM3 level
bsim4 SPICE format, BSIM4 level

5. 3. 4. Timing characterizations

.lib Synopsys Liberty Format
.tlf Cadence TLF format

5. 3. 5. Timing Constraints

.sdc Synopsys Design Constraints
.gcf Cadence Global Constraints Format
.inf Avertec Proprietary Constraints Format

5. 4. Output Files

5. 4. 1. Disassembly

.rep Contains a list of diagnostics (warnings and error messages) attributed to particular signals or transistors
.cns Contains the cone view of the circuit. Used for debugging
.cnv Contains the cone view of the circuit. Used for debugging

5. 4. 2. Timing Database Generation

The standard output of HITAS is the entire timing view of the circuit, called Unified Timing Database (UTD). It consists of text files suitable for the static timing analysis (timing constraints check), crosstalk analysis and timing abstraction. The UTD is made of the following files:

.dtx cone and RC timing arcs
.stm timing models relative to timing arcs (both cone and paths)
.rcx RC networks relative to RC timing arcs
.loop combinational loops detected in the circuit

5. 4. 3. Static Timing Analysis

.str slack report
.sto switching windows calculated for all reference points
.ste warnings encountered during static timing analysis (such as latches with no clock)

5. 4. 4. Crosstalk Analysis

.ctk human readable file containing crosstalk related information, such as noise levels and aggressors contributions
.ctx file containing all the delays calculated with crosstalk effects of a complete design hierarchy

5. 4. 5. Abstraction

.lib Timing abstraction in Synopsys Liberty format
.tlf3 Timing abstraction in Cadence TLF3 format
.tlf4 Timing abstraction in Cadence TLF4 format