12. Analog Sub-circuit Characterization

12. 1. Objective

HITAS is designed to compute propagation delays in digital designs. The advantage of this restrictive target is to enable very fast computing times. The drawback is that non-digital block characterization is not directly handled by HITAS and should be supplied to 3rd-party analog simulators. However, HITAS provides various ways to link with external characterizations.

First, the tool provides the means to choose between integrating a pre-characterization (such as a .lib or .dtx file) and integrating an on-the-fly characterization (by piloting an analog simulator).

The pre-characterization strategy is easier to set-up, but has the drawback to provide only one characterization for (potentially) several instances of an analog sub-circuit. The on-the-fly characterization is a little more difficult to set-up, but provides environment-dependant (PVT, input slopes, output loads) characterizations, and therefore greater accuracy.

Second, the tool is able to integrate the characterizations within either a pre-layout or a post-layout timing analysis.

In a pre-layout timing analysis, the source netlist is hierarchical. With appropriate directives, the tool just ignores the analog sub-circuits during the parse of the netlist. It then constructs the timing database on the remaining only-digital netlist, and fills the "analog holes" with either pre- or on-the-fly characterization.

In a post-layout timing analysis, the situation is a little trickier, as the source netlist is the most often a flat-transistor netlist (if the extracted netlist is hierarchical, the integration process is just the same as in a pre-layout timing analysis). The challenge is here to identify in the top-level netlist the transistors that belong to the analog sub-circuits, in order to ignore them and create the "analog holes" and the remaining only-digital netlist. Assuming that the pre-layout netlist of the analog sub-circuit exists, the identification in the top-level netlist of the transistors that belong to that sub-circuit is done by pattern matching.

12. 2. Pre-Characterization

In this section, we present how to create a DTX file within a Tcl script, and how to get timing values from analog simulation results. We then present how to integrate this pre-characterization in the top-level timing database construction, the latest either being based upon a hierarchical or flat transistor netlist.

The pre-characterization approach implies that this DTX file should be created before invoking HITAS on the entire design.

12. 2. 1. Database Construction

The API functions provided with the avt_shell Tcl interface enable the creation of custom timing databases (DTX files). We will just present here a few of those functions , as well as the global construction mechanism.

The ttv_CreateTimingFigure function creates the timing database itself. The function takes a netlist as argument, and builds the interface of the new timing database upon the interface of the netlist provided. If the new timing database is intended to replace an analog sub-circuit, it ensures interface consistency between the "hole" in the top-level netlist and the newly created timing database. Note that the Vdd and Vss names must be specified if they appear on the interface.

The ttv_AddTiming functions add timing arcs in the database.

The ttv_FinishTimingFigure function updates the database.

The ttv_DriveTimingFigure function prints the database on disk (DTX file).

See HITAS Tutorial for example.

12. 2. 2. Simulator Linking

The construction script described above associates "hard" values to the delays and slopes given as parameters of the ttv_AddTiming function (timing arc creation). It is the responsibility of the user to associate pertinent values to the parameters of the ttv_AddTiming function, by all the ways Tcl scripting provides.

However, the avt_shell Tcl interface also provides means to retrieve the values from analog simulations results. Provided functions cover:

All these functions require the same configuration as the one required for SPICE deck generation. See HITAS Tutorial for example.

12. 2. 3. Hierarchical Netlist Integration (Pre-Layout)

The first step to perform when integrating the pre-characterized DTX file within a hierarchical netlist is the blackboxing of the instances of the analog sub-circuits, in order to obtain "analog holes" in the netlist. This is done with the avt_SetBlackBoxes function, taking as argument the list of the sub-circuits to blackbox.

The default behavior of HITAS is not to try to fill the "holes". To tell the tool to fill the holes with timing characterizations, the tasIgnoreBlackbox variable should be set to yes

The timing arcs for the instances rs_clock_gen are directly integrated in the new database.

See HITAS Tutorial for example.

12. 2. 4. Flat Netlist Integration (Post-Layout)

Obtaining the "analog holes" for a flat netlist is a little more difficult than for a hierarchical netlist, as the blackboxing mechanism can not be applied. In order to create these holes, HITAS uses a method based on pattern-matching (the GNS pattern-matching engine). User must provide a transistor pattern (i.e. a transistor level netlist) of the analog sub-circuit which should be substituted by a custom timing database. The most common way is to provide the tool with the schematic SPICE netlist of the analog sub-circuit. The tool then tries to identify the set of transistors in the top-level netlist that matches the provided pattern. The tool then removes those transistors from the top-level netlist, thus creating the "analog holes".

The following steps must be performed to activate the pattern-matching method:

If HITAS is invoked with the configuration set up to now, it will integrate the timing description (DTX file) of the "analog holes" corresponding to the removed transistors matching the given pattern.

12. 2. 5. Netlists Consistency

The pre-characterization process is the same in the case of a flat or hierarchical top-level netlist. It just requires the netlist of the analog sub-circuit to simulate, in order to obtain the appropriate values for the timing arcs.

When dealing with a hierarchical netlist, the user should provide a netlist of the analog sub-circuit coming from the same source as the top-level (schematic editor or hierarchical extractor). Thus both netlists contain (or not) parasitics, and the analysis is consistent.

When dealing with a flat netlist, it is most of the times in a post-layout approach. Actually, the only reason for using a flat netlist is that it is sometimes the only output parasitic extractors provide. In such a case, the top-level netlist contains parasitics, and one must take care that the netlist used for simulation of the analog sub-circuit also contains parasitics.

12. 3. On-the-Fly Characterization

The on-the-fly characterization follows the same principles as the pre-characterization, i.e.:

The difference is that the steps one and two are performed for each instance of the analog subcircuit, taking into account instantiation-specific parameters (output load). It then provides greater accuracy but implies a different implementation.

On-the-fly characterization is based upon the GNS pattern-matching engine. The methodology is to associate an "action" with a matching event i.e., each time the tool identifies a pattern in the top-level netlist, it executes the corresponding action. Here the corresponding action will be the steps one and two described above (link with an analog simulator and create a timing database of the analog sub-circuit).

The difference of implementation lies in the description language used to write the action. As the pre-characterization method uses the Tcl language, the writing of the "action" for on-the-fly characterization uses the C language. By the way, the prototypes of the functions used in both cases are identical.

An action is then typically a C file. The association of an "action" with a pattern takes place in the LIBRARY file.

12. 3. 1. Database Construction

Apart from the syntax, the C file used for simulator link and database creation is very close to the Tcl script used for pre-characterization.

12. 3. 2. Hierarchical Netlist Integration (Pre-Layout)

The integration of on-the-fly characterization in a hierarchical netlist uses a combination of the blackboxing and pattern-matching mechanisms.

The remaining configuration is the same as in the approach of integration of a pre-characterization in a flat netlist.

12. 3. 3. Flat Netlist Integration (Post-Layout)

The integration of on-the-fly characterization in a flat netlist also uses a combination of the blackboxing and pattern-matching mechanisms. Here, the "analog holes" are created by the pattern matching mechanism itself, as in the integration of a pre-characterization in a flat netlist approach. The blackboxing configuration (tasIgnoreBlackbox) should not be used. However, it will have no effect on the netlist itself (as there is no instance to blackbox), but it may have a side effect on the sub-circuit provided for the pattern matching engine (if the name of the latest appears in the avt_SetBlackBoxes function, it may be unintentionally blackboxed, making the pattern matching process to fail).

The main advantage of on-the-fly characterization is to provide a specific timing database for each instance of an analog sub-circuit, depending on instantiation context (e.g. output load). Another advantage of the on-the-fly approach is that the analog simulations are performed on the transistors of the sub-circuit matching the pattern provided. Therefore each instance matching the pattern has its own parasitic information.