� ���o8��( ���.firefly,firefly-rk3288-reloadrockchip,rk3288&7Firefly-RK3288-reloadaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000�/serial@ff190000�/serial@ff690000�/serial@ff1b0000�/serial@ff1c0000�/spi@ff110000�/spi@ff120000�/spi@ff130000arm-pmuarm,cortex-a12-pmu0������cpus�rockchip,rk3066-smp�cpu@500�cpuarm,cortex-a12��'�@5< Hcpu@501�cpuarm,cortex-a12��'�@5Hcpu@502�cpuarm,cortex-a12��'�@5Hcpu@503�cpuarm,cortex-a12��'�@5Hcpu-opp-tableoperating-points-v2PHopp-126000000[���b ��opp-216000000[ ��b ��opp-312000000[��b ��opp-408000000[Q�b ��opp-600000000[#�Fb ��opp-696000000[)|b~�opp-816000000[0�,bB@opp-1008000000[<�b�opp-1200000000[G��b��opp-1416000000[TfrbO�opp-1512000000[ZJb� opp-1608000000[_�"b�pamba simple-buspdma-controller@ff250000arm,pl330arm,primecell��%@�w�5� �apb_pclkH dma-controller@ff600000arm,pl330arm,primecell��`@�w�5� �apb_pclk �disableddma-controller@ffb20000arm,pl330arm,primecell���@�w�5� �apb_pclkHfreserved-memorypdma-unusable@fe000000��oscillator fixed-clock�n6�xin24m�H timerarm,armv7-timer�0�   �n6timer@ff810000rockchip,rk3288-timer���  �H 5 a �timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshc �р 5�Drv�biuciuciu-driveciu-sample � �� @��#reset�okay/9K\�nydefault� ��dwmmc@ff0d0000rockchip,rk3288-dw-mshc �р 5�Esw�biuciuciu-driveciu-sample �!�� @��#reset�okay/K�n��ydefault�������dwmmc@ff0e0000rockchip,rk3288-dw-mshc �р 5�Ftx�biuciuciu-driveciu-sample �"��@��#reset �disableddwmmc@ff0f0000rockchip,rk3288-dw-mshc �р 5�Guy�biuciuciu-driveciu-sample �#��@��#reset�okay/9n�ydefault���saradc@ff100000rockchip,saradc�� �$ 5I[�saradcapb_pclk�W #saradc-apb�okayH�spi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5AR�spiclkapb_pclk2 7txrx �,ydefault�!"#$�� �disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BS�spiclkapb_pclk2 7txrx �-ydefault�%&'(�� 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���������gpu_thermalXdn�|8tripsgpu_alert0�p���passiveH;gpu_crit�_��� �criticalcooling-mapsmap0�; ���������tsadc@ff280000rockchip,rk3288-tsadc��( �%5HZ�tsadcapb_pclk�� #tsadc-apbyinitdefaultsleep�<�=�<��s�okay�H8ethernet@ff290000rockchip,rk3288-gmac��)�*macirqeth_wake_irq:>85�fgc��]M�stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac�B #stmmaceth�okG�W?ninputydefault�@ABC{D�rgmii� �'B@ �E�0�usb@ff500000 generic-ehci��P �5��usbhost�F�usb �disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2��T �5��otg�host�G �usb2-phy�okayydefault�Husb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2��X �5��otg�otg���@@ �I �usb2-phy�okayusb@ff5c0000 generic-ehci��\ �5��usbhost �disabledi2c@ff650000rockchip,rk3288-i2c��e �<�i2c5Lydefault�J�okay��syr827@40silergy,syr827#�@@vdd_cpuO �Pg�p��,�@�KH syr828@41silergy,syr828#�A@vdd_gpuO �Pg�p�Kact8846@5aactive-semi,act8846�Zydefault�LM��KKKK%K1K=NregulatorsREG1@vcc_ddrOO�gO�REG2@vcc_ioO2Z�g2Z�HREG3@vdd_logO��g��REG4@vcc_20O��g��HNREG5 @vccio_sdO2Z�g2Z�HREG6 @vdd10_lcdOB@gB@REG7@vcca_18Ow@gw@REG8@vcca_33O2Z�g2Z�HRREG9 @vcca_lanO2Z�g2Z�HDREG10@vdd_10OB@gB@REG11@vcc_18Ow@gw@HREG12 @vcc18_lcdOw@gw@hym8563@51haoyu,hym8563�Q����xin32k&O�ydefault�PH�i2c@ff660000rockchip,rk3288-i2c��f �=�i2c5Nydefault�Q�okayes8328@10everest,es8328IRURaRmR5�R�i2s_hclki2s_clk�pwm@ff680000rockchip,rk3288-pwm��hzydefault�S5^�pwm �disabledpwm@ff680010rockchip,rk3288-pwm��hzydefault�T5^�pwm �disabledpwm@ff680020rockchip,rk3288-pwm��h zydefault�U5^�pwm �disabledpwm@ff680030rockchip,rk3288-pwm��h0zydefault�V5^�pwm �disabledbus_intmem@ff700000 mmio-sram��p�p�p�smp-sram@0rockchip,rk3066-smp-sram�sram@ff720000#rockchip,rk3288-pmu-srammmio-sram��rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd��sHpower-controller!rockchip,rk3288-power-controller�GhW Hipd_vio@9� �5��������������chgfdehilkj$�WXYZ[\]^_pd_hevc@11� 5�op�`apd_video@12� 5���bpd_gpu@13� 5��cdreboot-modesyscon-reboot-mode���RB��RB��RB� �RB�syscon@ff740000rockchip,rk3288-sgrfsyscon��tclock-controller@ff760000rockchip,rk3288-cru��v:>��HG��j��k$�#g��ׄ�e��рxh���рxh�Hsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd��wH>edp-phyrockchip,rk3288-dp-phy5h�24m� �disabledHyio-domains"rockchip,rk3288-io-voltage-domain�okay !e,:DHVfr�usbphyrockchip,rk3288-usb-phy�okayusb-phy@320�� 5]�phyclk�HIusb-phy@334��45^�phyclk�HFusb-phy@348��H5_�phyclk�HGwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt���5p �O�okaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif���� �hclkmclk5�T2f7tx �6ydefault�g:>�okayH�i2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s���� �52ff7txrx�i2s_hclki2s_clk5�Rydefault�h���okaycypto-controller@ff8a0000rockchip,rk3288-crypto���@ �0 5��}��aclkhclksclkapb_pclk�� #crypto-rst�okayiommu@ff900800rockchip,iommu���@ �*iep_mmu5�� �aclkiface� �disablediommu@ff914000rockchip,iommu ���@��P �*isp_mmu5�� �aclkiface�� �disabledrga@ff920000rockchip,rk3288-rga���� �5��j�aclkhclksclk�i �ilm #coreaxiahbvop@ff930000rockchip,rk3288-vop���� �5����aclk_vopdclk_vophclk_vop�i �def #axiahbdclkj�okayportH endpoint@0�kH~endpoint@1�lHzendpoint@2�mHtendpoint@3�nHwiommu@ff930300rockchip,iommu��� � *vopb_mmu5�� �aclkiface�i ��okayHjvop@ff940000rockchip,rk3288-vop���� �5����aclk_vopdclk_vophclk_vop�i ���� #axiahbdclko�okayportH endpoint@0�pHendpoint@1�qH{endpoint@2�rHuendpoint@3�sHxiommu@ff940300rockchip,iommu��� � *vopl_mmu5�� �aclkiface�i ��okayHomipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi���@ �5~d �refpclk�i :> �disabledportsportendpoint@0�tHmendpoint@1�uHrlvds@ff96c000rockchip,rk3288-lvds����@5g �pclk_lvdsylcdc�v�i :> �disabledportsport@0�endpoint@0�wHnendpoint@1�xHsdp@ff970000rockchip,rk3288-dp���@ �b5ic�dppclk�y�dp�o#dp:> �disabledportsport@0�endpoint@0�zHlendpoint@1�{Hqhdmi@ff980000rockchip,rk3288-dw-hdmi���K�:> �g5hmn�iahbisfrcec�i �okay|ydefault�}portsportendpoint@0�~Hkendpoint@1�Hpiommu@ff9a0800rockchip,iommu��� � *vpu_mmu5�� �aclkiface� �disablediommu@ff9c0440rockchip,iommu ���@@���@ �o *hevc_mmu5�� �aclkiface� �disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760���$� *jobmmugpu5���i  �disabledgpu-opp-tableoperating-points-v2H�opp@100000000[��b~�opp@200000000[ ��b~�opp@300000000[�bB@opp@400000000[ׄb��opp@500000000[�ebO�opp@600000000[#�Fb�qos@ffaa0000syscon��� Hcqos@ffaa0080syscon���� Hdqos@ffad0000syscon��� HXqos@ffad0100syscon��� HYqos@ffad0180syscon���� HZqos@ffad0400syscon��� H[qos@ffad0480syscon���� H\qos@ffad0500syscon��� HWqos@ffad0800syscon��� H]qos@ffad0880syscon���� H^qos@ffad0900syscon��� H_qos@ffae0000syscon��� Hbqos@ffaf0000syscon��� H`qos@ffaf0080syscon���� Hainterrupt-controller@ffc01000 arm,gic-400+@@����� ��@ ��`  � Hefuse@ffb40000rockchip,rk3288-efuse��� 5q �pclk_efusecpu_leakage@17�pinctrlrockchip,rk3288-pinctrl:>�pgpio0@ff750000rockchip,gpio-bank��u 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@vcc_otg_5vOLK@gLK@�Kdovdd-1v8-regulatorregulator-fixed � �� ydefault�� @dovdd_1v8Ow@gw@�Hevcc28-dvp-regulatorregulator-fixed � �� ydefault�� @vcc28_dvpO*��g*���af_28-regulatorregulator-fixed � �O ydefault�� @dvdd_1v2OO�gO��wifi-regulatorregulator-fixed@vbat_wlO2Z�g2Z��H #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclockscpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-sdio-irqmmc-pwrseqnon-removablesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-ddr50mmc-ddr-1_8vmmc-hs200-1_8v#io-channel-cellsdmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-enable-ramp-delayregulator-ramp-delayvin-supplysystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supplyDVDD-supplyAVDD-supplyPVDD-supplyHPVDD-supply#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltwakeup-sourcegpiospanic-indicatorlinux,default-triggerreset-gpiossimple-audio-card,namesound-daienable-active-highstartup-delay-us