� ��Y�8U�(�U� ,CSQ CS908 top set box2csq,cs908allwinner,sun6i-a31saliases=/soc/ethernet@1c30000G/soc/serial@1c28000chosen OVserial0:115200n8framebuffer-lcd0-hdmi02allwinner,simple-framebuffersimple-framebufferbde_be0-lcd0-hdmi@u3/2w�z�� |disabledframebuffer-lcd002allwinner,simple-framebuffersimple-framebuffer bde_be0-lcd00u3/w�z |disabledtimer2arm,armv7-timer0�   �n6�cpus�allwinner,sun6i-a31 cpu@02arm,cortex-a7�cpu�u��� �a�O� /O� ����SB@�cpu@12arm,cortex-a7�cpu�u��� �a�O� /O� ����SB@�cpu@22arm,cortex-a7�cpu�u��� �a�O� /O� ����SB@�cpu@32arm,cortex-a7�cpu�u��� �a�O� /O� ����SB@�thermal-zonescpu_thermal�,�:cooling-mapsmap0J0O��������������������������������tripscpu_alert0^pj��passivecpu_crit^��j� �criticalpmu2arm,cortex-a7-pmu0�xyz{clocks Oclk-24Mu 2fixed-clock�n6��P�osc24Mclk-32ku 2fixed-clock����P �ext_osc32k2clk-mii-phy-txu 2fixed-clock�}x@ �mii_phy_tx clk-gmac-int-txu 2fixed-clock�sY@ �gmac_int_tx clk@1c200d0u2allwinner,sun7i-a20-gmac-clk���u �gmac_txdisplay-engine$2allwinner,sun6i-a31s-display-engine�  |disabledsoc 2simple-bus Odma-controller@1c020002allwinner,sun6i-a31-dma��  �2u��lcd-controller@1c0c0002allwinner,sun6i-a31s-tcon��� �V��lcdu/��ahbtcon-ch0tcon-ch1�tcon0-pixel-clockuports port@0 �endpoint@0�� 0endpoint@1��*port@1 �endpoint@1���lcd-controller@1c0d0002allwinner,sun6i-a31-tcon��� �W��lcdu0���ahbtcon-ch0tcon-ch1�tcon1-pixel-clockuports port@0 �endpoint@0��1endpoint@1��+port@1 �endpoint@1���mmc@1c0f0002allwinner,sun7i-a20-mmc��� uOQP�ahbmmcoutputsample��ahb �< default |disabled mmc@1c100002allwinner,sun7i-a20-mmc�� uRTS�ahbmmcoutputsample��ahb �= default |disabled mmc@1c110002allwinner,sun7i-a20-mmc�� uUWV�ahbmmcoutputsample��ahb �> |disabled mmc@1c120002allwinner,sun7i-a20-mmc��  uXZY�ahbmmcoutputsample� �ahb �? |disabled hdmi@1c160002allwinner,sun6i-a31-hdmi��` �X(u2�� �ahbmodddcpll-0pll-1��ahb!ddc-txddc-rxaudio-tx+   |disabledports port@0 �endpoint@0��endpoint@1��port@1�usb@1c190002allwinner,sun6i-a31-musb���u(� �G0mc@EusbOVhost|okayphy@1c194002allwinner,sun6i-a31-usb-phy�������^phy_ctrlpmu1pmu2udef�usb0_phyusb1_phyusb2_phy�!�usb0_resetusb1_resetusb2_reset|okayhusb@1c1a000&2allwinner,sun6i-a31-ehcigeneric-ehci��� �Hu)�@Eusb|okayusb@1c1a400&2allwinner,sun6i-a31-ohcigeneric-ohci��� �Iu+g�@Eusb |disabledusb@1c1b000&2allwinner,sun6i-a31-ehcigeneric-ehci��� �Ju*�@Eusb|okayusb@1c1b400&2allwinner,sun6i-a31-ohcigeneric-ohci��� �Ku,h�@Eusb|okayusb@1c1c400&2allwinner,sun6i-a31-ohcigeneric-ohci��� �Mu-i� |disabledclock@1c200002allwinner,sun6i-a31-ccu�� u �hoscloscuspinctrl@1c208002allwinner,sun6i-a31s-pinctrl��0� u@�apbhosclosc����gmac-gmii-pins��PA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27�gmac�gmac-mii-pinsT�PA0PA1PA2PA3PA8PA9PA11PA12PA13PA14PA19PA20PA21PA22PA23PA24PA26PA27�gmac gmac-rgmii-pinsF�PA0PA1PA2PA3PA9PA10PA11PA12PA13PA14PA19PA20PA25PA26PA27�gmac�(i2c0-pins �PH14PH15�i2c0i2c1-pins �PH16PH17�i2c1i2c2-pins �PH18PH19�i2c2lcd0-rgb888-pins��PD0PD1PD2PD3PD4PD5PD6PD7PD8PD9PD10PD11PD12PD13PD14PD15PD16PD17PD18PD19PD20PD21PD22PD23PD24PD25PD26PD27�lcd0mmc0-pins�PF0PF1PF2PF3PF4PF5�mmc0��mmc1-pins�PG0PG1PG2PG3PG4PG5�mmc1��mmc2-4bit-pins�PC6PC7PC8PC9PC10PC11�mmc2��mmc2-8bit-emmc-pins3�PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC24�mmc2��mmc3-8bit-emmc-pins3�PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC24�mmc3�(�spdif-tx-pin�PH28�spdifuart0-ph-pins �PH20PH21�uart0timer@1c20c002allwinner,sun4i-a10-timer�� �H�uwatchdog@1c20ca02allwinner,sun6i-a31-wdt�� �  �uspdif@1c21000�2allwinner,sun6i-a31-spdif�� � u>c�+ �apbspdif+!rxtx |disabledi2s@1c22000�2allwinner,sun6i-a31-i2s��  � uAa�-�apbmod+!rxtx |disabledi2s@1c22400�2allwinner,sun6i-a31-i2s��$ �uBb�.�apbmod+!rxtx |disabledlradc@1c228002allwinner,sun4i-a10-lradc-keys��( � |disabledrtp@1c250002allwinner,sun6i-a31-ts��P ��serial@1c280002snps,dw-apb-uart�€ �uG�3+!rxtx|okay defaultserial@1c284002snps,dw-apb-uart�„ �uH�4+!rxtx |disabledserial@1c288002snps,dw-apb-uart�ˆ �uI�5+!rxtx |disabledserial@1c28c002snps,dw-apb-uart�Œ �uJ�6+  !rxtx |disabledserial@1c290002snps,dw-apb-uart� �uK�7+  !rxtx |disabledserial@1c294002snps,dw-apb-uart�” �uL�8+!rxtx |disabledi2c@1c2ac002allwinner,sun6i-a31-i2c�¬ �uC�/ default |disabled i2c@1c2b0002allwinner,sun6i-a31-i2c�° �uD�0 default |disabled i2c@1c2b4002allwinner,sun6i-a31-i2c�´ �uE�1 default |disabled i2c@1c2b8002allwinner,sun6i-a31-i2c�¸ � uF�2 |disabled ethernet@1c300002allwinner,sun7i-a20-gmac��T �R0macirq u!�stmmacethallwinner_gmac_tx�  �stmmaceth*3D|okay default [!fmiimdio2snps,dwmac-mdio ethernet-phy@1�!crypto-engine@1c1500062allwinner,sun6i-a31-cryptoallwinner,sun4i-a10-crypto��P �Pu\�ahbmod��ahbcodec@1c22c00�2allwinner,sun6i-a31-codec��, �u=� �apbcodec�*+!rxtx |disabledtimer@1c6000082allwinner,sun6i-a31-hstimerallwinner,sun7i-a20-hstimer��0�3456u#�spi@1c680002allwinner,sun6i-a31-spi�ƀ �Au$]�ahbmod+!rxtx� |disabled spi@1c690002allwinner,sun6i-a31-spi�Ɛ �Bu%^�ahbmod+!rxtx� |disabled spi@1c6a0002allwinner,sun6i-a31-spi�Ơ �Cu&_�ahbmod+!rxtx� |disabled spi@1c6b0002allwinner,sun6i-a31-spi�ư �Du'`�ahbmod+!rxtx� |disabled interrupt-controller@1c81000 2arm,gic-400 ��� �@ �` �� � display-frontend@1e00000%2allwinner,sun6i-a31-display-frontend�� �]u5|u �ahbmodram�! ports port@1 �endpoint@0��",endpoint@1��#&display-frontend@1e20000%2allwinner,sun6i-a31-display-frontend�� �^u6}v �ahbmodram�" ports port@1 �endpoint@0��$-endpoint@1��%'display-backend@1e40000$2allwinner,sun6i-a31-display-backend�� �`u4{x �ahbmodram� o{�ports port@0 �endpoint@0��&#endpoint@1��'%port@1 �endpoint@1��()drc@1e500002allwinner,sun6i-a31-drc�� �[u<�r �ahbmodram�(o��ports port@0 �endpoint@1��)(port@1 �endpoint@0��*endpoint@1��+display-backend@1e60000$2allwinner,sun6i-a31-display-backend�� �_u3zw �ahbmodram�oz�ports port@0 �endpoint@0��,"endpoint@1��-$port@1�endpoint�./drc@1e700002allwinner,sun6i-a31-drc�� �[u;�q �ahbmodram�'o��ports port@0�endpoint�/.port@1 �endpoint@0��0 endpoint@1��1rtc@1f00000u2allwinner,sun6i-a31-rtc��T�()u2�osc32kinterrupt-controller@1f00c002allwinner,sun6i-a31-r-intc����  � prcm@1f014002allwinner,sun6i-a31-prcm��ar100_clk2allwinner,sun6i-a31-ar100-clkuu  �ar1003ahb0_clk2fixed-factor-clocku��u3�ahb04apb0_clk2allwinner,sun6i-a31-apb0-clkuu4�apb05apb0_gates_clk#2allwinner,sun6i-a31-apb0-gates-clkuu5D�apb0_pioapb0_irapb0_timerapb0_p2wiapb0_uartapb0_1wireapb0_i2c6ir_clku2allwinner,sun4i-a10-mod0-clk u�ir7apb0_rst 2allwinner,sun6i-a31-clock-resets8cpucfg@1f01c002allwinner,sun6i-a31-cpuconfig��ir@1f020002allwinner,sun6i-a31-ir u67�apbir�8 �%�� @|okay default9pinctrl@1f02c002allwinner,sun6i-a31-r-pinctrl��,�-.u6�apbhosclosc�8����s-ir-rx-pin�PL4�s_ir9s-p2wi-pins�PL0PL1�s_p2wi:i2c@1f034002allwinner,sun6i-a31-p2wi��4 �'u6����8 default: |disabled  interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0serial0rangesstdout-pathallwinner,pipelineclocksstatusinterruptsclock-frequencyarm,cpu-registers-not-fw-configuredenable-methoddevice_typeregclock-latencyoperating-points#cooling-cellsphandlepolling-delay-passivepolling-delaythermal-sensorstripcooling-devicetemperaturehysteresis#clock-cellsclock-accuracyclock-output-namesallwinner,pipelinesresets#dma-cellsreset-namesclock-namesremote-endpointallwinner,tcon-channelpinctrl-namespinctrl-0dma-namesdmasinterrupt-namesphysphy-namesextcondr_modereg-names#phy-cells#reset-cellsgpio-controllerinterrupt-controller#interrupt-cells#gpio-cellspinsfunctiondrive-strengthbias-pull-up#sound-dai-cells#thermal-sensor-cellsreg-shiftreg-io-widthsnps,pblsnps,fixed-burstsnps,force_sf_dma_modephy-handlephy-modeassigned-clocksassigned-clock-ratesclock-divclock-mult