� ��}�8u�(�u�$mediatek,mt8173-evbmediatek,mt8173 +!7MediaTek MT8173 evaluation boardaliases=/soc/ovl@1400c000B/soc/ovl@1400d000G/soc/rdma@1400e000M/soc/rdma@1400f000S/soc/rdma@14010000Y/soc/wdma@14011000_/soc/wdma@14012000e/soc/color@14013000l/soc/color@14014000s/soc/split@14018000z/soc/split@14019000�/soc/dpi@1401d000�/soc/dsi@1401b000�/soc/dsi@1401c000�/soc/rdma@14001000�/soc/rdma@14002000�/soc/rsz@14003000�/soc/rsz@14004000�/soc/rsz@14005000�/soc/wdma@14006000�/soc/wrot@14007000�/soc/wrot@14008000�/soc/serial@11002000�/soc/serial@11003000�/soc/serial@11004000�/soc/serial@11005000opp_table0operating-points-v2� opp-50700000084� xopp-702000000)׫� ��opp-1001000000;� @��opp-1105000000A��@ehopp-1209000000H�@�opp-1300000000M|m �opp-1508000000Y�A�opp-1703000000e���*�opp_table1operating-points-v2� opp-50700000084� �`opp-702000000)׫� :�opp-1001000000;� @%opp-1209000000H�@�@opp-1404000000S�W]�opp-1612000000`+�opp-1807000000k�����opp-2106000000}��*�cpus+cpu-mapcluster0core0%core1%cluster1core0%core1%cpu@0)cpuarm,cortex-a5359psciGWf mcpuintermediatey � cpu@1)cpuarm,cortex-a5359psciGWf mcpuintermediatey � cpu@100)cpuarm,cortex-a7259psciGWfmcpuintermediatey � � cpu@101)cpuarm,cortex-a7259psciGWfmcpuintermediatey � � idle-states�pscicpu-sleep-0arm,idle-state�����@�pmu_a53arm,cortex-a53-pmu  pmu_a72arm,cortex-a72-pmu  psci#arm,psci-1.0arm,psci-0.2arm,psci@smc*�6�>�oscillator0 fixed-clockER���bclk26moscillator1 fixed-clockER}bclk32koscillator2 fixed-clockERbcpum_ckthermal-zonescpu_thermalu������tripstrip-point0� ���0passivetrip-point1�L��0passivecpu_crit0��8�� 0criticalcooling-mapsmap0��� map1���reserved-memory+�vpu_dma_mem_region@b7000000shared-dma-pool5�P�timerarm,armv8-timer 0    soc+ simple-bus�clock-controller@10000000mediatek,mt8173-topckgen5Epower-controller@10001000 mediatek,mt8173-infracfgsyscon5E power-controller@10003000mediatek,mt8173-pericfgsyscon50E syscfg_pctl_a@10005000%mediatek,mt8173-pctl-a-syscfgsyscon5Ppinctrl@1000b000mediatek,mt8173-pinctrl5�-?O[p$ ���xxx@pins1���i2c0pins1�-.�i2c1pins1�}~�i2c2 pins1�+,�i2c3$pins1�jk�i2c4%pins1����i2c6&pins1�de�disp_pwm0_pins>pins1�W�mmc0default'pins_cmd_dat$�9:;<=>?@B��pins_clk�A�pins_rst�D�mmc1default+pins_cmd_dat�IJKLN���fpins_clk�M��pins_insert���mmc0(pins_cmd_dat$�9:;<=>?@B���epins_clk�A��epins_rst�D�mmc1,pins_cmd_dat�IJKLN���fpins_clk�M��fusb_iddig_pull_up5pins_iddig��usb_iddig_pull_down6pins_iddig��spi0!pins_spi�EFGHscpsys@10006000mediatek,mt8173-scpsys�5`fUXimmfgmmvencvenc_lt�watchdog@10007000(mediatek,mt8173-wdtmediatek,mt6589-wdt5ptimer@10008000,mediatek,mt8173-timermediatek,mt6577-timer5�  �f xpwrap@1000d000mediatek,mt8173-pwrap5��pwrap  ��pwrapf   mspiwrapmt6397mediatek,mt6397  [pmt6397regulatormediatek,mt6397-regulatorbuck_vpca15  buck_vpca155vpca15D �`\�pt0�� buck_vpca7  buck_vpca75vpca7D �`\�pt0��sbuck_vsramca15 buck_vsramca15 5vsramca15D �`\�pt0��buck_vsramca7 buck_vsramca7 5vsramca7D �`\�pt0�� buck_vcore  buck_vcore5vcoreD �`\�pt0��buck_vgpu  buck_vgpu5vgpuD �`\�pt0��sbuck_vdrm  buck_vdrm5vdrmDO�\\�t0��buck_vio18  buck_vio185vio18D� \6`t0��*ldo_vtcxo  ldo_vtcxo5vtcxo�ldo_va28  ldo_va285va28�ldo_vcama  ldo_vcama5vcamaD�`\*����ldo_vio28  ldo_vio285vio28�ldo_vusb  ldo_vusb5vusb2ldo_vmc ldo_vmc5vmcDw@\2Z���.ldo_vmch  ldo_vmch5vmchD-��\2Z���-ldo_vemc3v3  ldo_vemc3v3 5vemc_3v3D-��\2Z���)ldo_vgp1  ldo_vgp15vcamdD��\2Z���ldo_vgp2  ldo_vgp25vcamioDB@\2Z���ldo_vgp3  ldo_vgp35vcamafDO�\2Z���ldo_vgp4  ldo_vgp45vgp4DO�\2Z���ldo_vgp5  ldo_vgp55vgp5DO�\-����ldo_vgp6  ldo_vgp65vgp6DO�\2Z���ldo_vibr  ldo_vibr5vibrD� \2Z���cec@10013000mediatek,mt8173-cec50�  �f �okayvpu@10020000mediatek,mt8173-vpu 5 �tcmcfg_reg  �fgmmain�:intpol-controller@10200620.mediatek,mt8173-sysirqmediatek,mt6577-sysirq[p 5  iommu@10205000mediatek,mt8173-m4u5 P  �fmbclk��9efuse@10206000mediatek,mt8173-efuse5 `+calib@5285( #clock-controller@10209000mediatek,mt8173-apmixedsys5 �Ehdmi-phy@10209100mediatek,mt8173-hdmi-phy5 �$fmpll_refbhdmitx_dig_cts� �E �okayAmailbox@10212000mediatek,mt8173-gce5!   �fmgcemipi-dphy@10215000mediatek,mt8173-mipi-tx5!Pf bmipi_tx0_pllE  �disabled;mipi-dphy@10216000mediatek,mt8173-mipi-tx5!`f bmipi_tx1_pllE  �disabled<interrupt-controller@10221000 arm,gic-400p [@5"" "@ "`    auxadc@11001000mediatek,mt8173-auxadc5fmmain""serial@11002000*mediatek,mt8173-uartmediatek,mt6577-uart5   Sf$ mbaudbus�okayserial@11003000*mediatek,mt8173-uartmediatek,mt6577-uart50  Tf% mbaudbus �disabledserial@11004000*mediatek,mt8173-uartmediatek,mt6577-uart5@  Uf& mbaudbus �disabledserial@11005000*mediatek,mt8173-uartmediatek,mt6577-uart5P  Vf' mbaudbus �disabledi2c@11007000mediatek,mt8173-i2c 5pp�  L4f  mmaindma>defaultL+ �disabledi2c@11008000mediatek,mt8173-i2c 5�p��  M4f  mmaindma>defaultL+�okayda9211@68 dlg,da92115hregulatorsBUCKA5VBUCKAD �`\�0V��mC#�t'� BUCKB5VBUCKBD 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Jfu msourcehclk �disabledusb@11271000mediatek,mt8173-mtu3 5'0( �macippc  @�/01 f^msys_ckref_ck �+��okay23+42otg:>defaultid_floatid_groundL55H6xhci@11270000mediatek,mt8173-xhci5'�mac  s f^msys_ckref_ck�okay27usb-phy@11290000mediatek,mt8173-u3phy5)+��okayusb-phy@112908005)fmref �okay/usb-phy@112909005) fmref �okay0usb-phy@112910005)fmref �okay1clock-controller@14000000mediatek,mt8173-mmsyssyscon5�URׄE8rdma@14001000-mediatek,mt8173-mdp-rdmamediatek,mt8173-mdp5f88g9n|:rdma@14002000mediatek,mt8173-mdp-rdma5 f88g9�nrsz@14003000mediatek,mt8173-mdp-rsz50f8rsz@14004000mediatek,mt8173-mdp-rsz5@f8rsz@14005000mediatek,mt8173-mdp-rsz5Pf8wdma@14006000mediatek,mt8173-mdp-wdma5`f8 g9nwrot@14007000mediatek,mt8173-mdp-wrot5pf8 g9nwrot@14008000mediatek,mt8173-mdp-wrot5�f8 g9�novl@1400c000mediatek,mt8173-disp-ovl5�  �f8g9novl@1400d000mediatek,mt8173-disp-ovl5�  �f8g9�nrdma@1400e000mediatek,mt8173-disp-rdma5�  �f8g9nrdma@1400f000mediatek,mt8173-disp-rdma5�  �f8g9�nrdma@14010000mediatek,mt8173-disp-rdma5  �f8g9�nwdma@14011000mediatek,mt8173-disp-wdma5  �f8g9nwdma@14012000mediatek,mt8173-disp-wdma5   �f8g9�ncolor@14013000mediatek,mt8173-disp-color50  �f8color@14014000mediatek,mt8173-disp-color5@  �f8aal@14015000mediatek,mt8173-disp-aal5P  �f8gamma@14016000mediatek,mt8173-disp-gamma5`  �f8merge@14017000mediatek,mt8173-disp-merge5pf8split@14018000mediatek,mt8173-disp-split5�f8split@14019000mediatek,mt8173-disp-split5�f8ufoe@1401a000mediatek,mt8173-disp-ufoe5�  �f8dsi@1401b000mediatek,mt8173-dsi5�  �f8$8%;menginedigitalhs�;�dphy �disableddsi@1401c000mediatek,mt8173-dsi5�  �f8&8'<menginedigitalhs�<�dphy �disableddpi@1401d000mediatek,mt8173-dpi5�  �f8(8)mpixelenginepll�okayportendpoint�=Bpwm@1401e0002mediatek,mt8173-disp-pwmmediatek,mt6595-disp-pwm5��f8!8 mmainmm�okay>defaultL>pwm@1401f0002mediatek,mt8173-disp-pwmmediatek,mt6595-disp-pwm5��f8#8"mmainmm �disabledmutex@14020000mediatek,mt8173-disp-mutex5  �f8larb@14021000mediatek,mt8173-smi-larb5�?f88mapbsmismi@14022000mediatek,mt8173-smi-common5 f88mapbsmi?od@14023000mediatek,mt8173-disp-od50f8hdmi@14025000mediatek,mt8173-hdmi5P  � f8,8-8.8/mpixelpllbclkspdif>defaultL@�A�hdmi�8 �s�A�okayports+port@05endpoint�B=port@15endpoint�CHlarb@14027000mediatek,mt8173-smi-larb5p�?f8282mapbsmiclock-controller@15000000mediatek,mt8173-imgsyssyscon5EDlarb@15001000mediatek,mt8173-smi-larb5�?fDDmapbsmiclock-controller@16000000mediatek,mt8173-vdecsyssyscon5EEvcodec@16000000mediatek,mt8173-vcodec-dec�5 0@Phpx�  �n@g9 9!9%9&9'9"9#9$|:@f >lWMiNZmvcodecpllunivpll_d2clk_cci400_selvdec_selvdecpllvencpllvenc_lt_selvdec_bus_clk_src(�ilW �N>MRXU��/�larb@16010000mediatek,mt8173-smi-larb5�?fEEmapbsmiclock-controller@18000000mediatek,mt8173-vencsyssyscon5EFlarb@18001000mediatek,mt8173-smi-larb5�?fFFmapbsmivcodec@18002000mediatek,mt8173-vcodec-enc 5   ��n�g9`9a9b9c9d9i9j9k9l9m9n9�9�9�9�9�9�9�9�9�|: fPX?i2mvenc_sel_srcvenc_selvenc_lt_sel_srcvenc_lt_sel�Xi�MNclock-controller@19000000!mediatek,mt8173-vencltsyssyscon5EGlarb@19001000mediatek,mt8173-smi-larb5�?fGGmapbsmimemory@40000000)memory5@�chosenconnectorhdmi-connector�hdmi0dportendpoint�HCextcon_iddiglinux,extcon-usb-gpio �4regulator@0regulator-fixed 5usb_vbusDLK@\LK@ ���7regulator@1regulator-fixed5vbusDLK@\LK@ � �3 compatibleinterrupt-parent#address-cells#size-cellsmodelovl0ovl1rdma0rdma1rdma2wdma0wdma1color0color1split0split1dpi0dsi0dsi1mdp_rdma0mdp_rdma1mdp_rsz0mdp_rsz1mdp_rsz2mdp_wdma0mdp_wrot0mdp_wrot1serial0serial1serial2serial3opp-sharedphandleopp-hzopp-microvoltcpudevice_typeregenable-methodcpu-idle-states#cooling-cellsclocksclock-namesoperating-points-v2proc-supplysram-supplyentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paraminterruptsinterrupt-affinitycpu_suspendcpu_offcpu_on#clock-cellsclock-frequencyclock-output-namespolling-delay-passivepolling-delaythermal-sensorssustainable-powertemperaturehysteresistripcooling-devicecontributionrangesalignmentno-map#reset-cellsmediatek,pctl-regmappins-are-numberedgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinmuxinput-enablebias-pull-downbias-disableoutput-lowbias-pull-updrive-strength#power-domain-cellsinfracfgreg-namesresetsreset-namespower-domainsregulator-compatibleregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-enable-ramp-delaystatusmemory-regionmediatek,larbs#iommu-cellsmediatek,ibiasmediatek,ibias_up#phy-cells#mbox-cells#io-channel-cellsclock-divpinctrl-namespinctrl-0regulator-min-microampregulator-max-microampmediatek,pad-select#thermal-sensor-cellsmediatek,auxadcmediatek,apmixedsysnvmem-cellsnvmem-cell-namesassigned-clocksassigned-clock-parentspinctrl-1bus-widthmax-frequencycap-mmc-highspeedmediatek,hs200-cmd-int-delaymediatek,hs400-cmd-int-delaymediatek,hs400-cmd-resp-sel-risingvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr25cd-gpiosphysmediatek,syscon-wakeupvusb33-supplyvbus-supplyextcondr_modewakeup-sourcepinctrl-2assigned-clock-ratesiommusmediatek,larbmediatek,vpuphy-namesphyremote-endpoint#pwm-cellsmediatek,smimediatek,syscon-hdmilabelid-gpioenable-active-high